154 lines
3.9 KiB
C
154 lines
3.9 KiB
C
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/********** Typedefs ************/
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/* EX stage mux settings */
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typedef enum { MUX_NONE, MUX_EX_A, MUX_EX_B, MUX_MEM_E,
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MUX_WB_M, MUX_WB_E } mux_source_t;
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/* Simulator operating modes */
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typedef enum { S_WEDGED, S_STALL, S_FORWARD } sim_mode_t;
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/* Pipeline stage identifiers for stage operation control */
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typedef enum { IF_STAGE, ID_STAGE, EX_STAGE, MEM_STAGE, WB_STAGE } stage_id_t;
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/********** Defines **************/
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/* Get ra out of one byte regid field */
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#define GET_RA(r) HI4(r)
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/* Get rb out of one byte regid field */
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#define GET_RB(r) LO4(r)
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/************ Global state declaration ****************/
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/* How many cycles have been simulated? */
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extern word_t cycles;
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/* How many instructions have passed through the EX stage? */
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extern word_t instructions;
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/* Both instruction and data memory */
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extern mem_t mem;
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/* Keep track of range of addresses that have been written */
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extern word_t minAddr;
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extern word_t memCnt;
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/* Register file */
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extern mem_t reg;
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/* Condition code register */
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extern cc_t cc;
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extern stat_t stat;
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/* Operand sources in EX (to show forwarding) */
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extern mux_source_t amux, bmux;
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/* Provide global access to current states of all pipeline registers */
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pipe_ptr pc_state, if_id_state, id_ex_state, ex_mem_state, mem_wb_state;
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/* Current States */
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extern pc_ptr pc_curr;
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extern if_id_ptr if_id_curr;
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extern id_ex_ptr id_ex_curr;
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extern ex_mem_ptr ex_mem_curr;
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extern mem_wb_ptr mem_wb_curr;
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/* Next States */
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extern pc_ptr pc_next;
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extern if_id_ptr if_id_next;
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extern id_ex_ptr id_ex_next;
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extern ex_mem_ptr ex_mem_next;
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extern mem_wb_ptr mem_wb_next;
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/* Pending updates to state */
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extern word_t cc_in;
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extern word_t wb_destE;
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extern word_t wb_valE;
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extern word_t wb_destM;
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extern word_t wb_valM;
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extern word_t mem_addr;
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extern word_t mem_data;
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extern bool_t mem_write;
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/* Intermdiate stage values that must be used by control functions */
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extern word_t f_pc;
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extern byte_t imem_icode;
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extern byte_t imem_ifun;
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extern bool_t imem_error;
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extern bool_t instr_valid;
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extern word_t d_regvala;
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extern word_t d_regvalb;
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extern word_t e_vala;
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extern word_t e_valb;
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extern bool_t e_bcond;
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extern bool_t dmem_error;
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/* Simulator operating mode */
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extern sim_mode_t sim_mode;
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/* Log file */
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extern FILE *dumpfile;
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/*************** Simulation Control Functions ***********/
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/* Bubble next execution of specified stage */
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void sim_bubble_stage(stage_id_t stage);
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/* Stall stage (has effect at next update) */
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void sim_stall_stage(stage_id_t stage);
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/* Sets the simulator name (called from main routine in HCL file) */
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void set_simname(char *name);
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/* Initialize simulator */
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void sim_init();
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/* Reset simulator state, including register, instruction, and data memories */
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void sim_reset();
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/*
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Run pipeline until one of following occurs:
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- A status error is encountered in WB.
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- max_instr instructions have completed through WB
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- max_cycle cycles have been simulated
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Return number of instructions executed.
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if statusp nonnull, then will be set to status of final instruction
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if ccp nonnull, then will be set to condition codes of final instruction
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*/
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word_t sim_run_pipe(word_t max_instr, word_t max_cycle, byte_t *statusp, cc_t *ccp);
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/* If dumpfile set nonNULL, lots of status info printed out */
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void sim_set_dumpfile(FILE *file);
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/*
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* sim_log dumps a formatted string to the dumpfile, if it exists
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* accepts variable argument list
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*/
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void sim_log( const char *format, ... );
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/******************* GUI Interface Functions **********************/
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#ifdef HAS_GUI
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void signal_sources();
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void signal_register_clear();
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void report_pc(unsigned fpc, unsigned char fpcv,
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unsigned dpc, unsigned char dpcv,
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unsigned epc, unsigned char epcv,
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unsigned mpc, unsigned char mpcv,
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unsigned wpc, unsigned char wpcv);
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void report_state(char *id, word_t current, char *txt);
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void show_cc(cc_t cc);
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void show_cpi();
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void show_stat(stat_t stat);
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void create_memory_display();
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void set_memory(word_t addr, word_t val);
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#endif
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